Sram cell with t-shaped contact

ABSTRACT

An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of application Ser. No. 12/479,266, filedJun. 5, 2009, the content of which is hereby incorporated by reference.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuits. Moreparticularly, this invention relates to SRAMs in integrated circuits.

DESCRIPTION OF THE VIEWS OF THE DRAWING

FIG. 1A through 1C are top views of a pair of cross-coupled inverters inan SRAM cell contained in an integrated circuit, in which T-shapedcontacts are formed according to a first embodiment.

FIG. 2A through 2C are top views of a pair of cross-coupled inverters inan SRAM cell contained in an integrated circuit, in which T-shapedcontacts are formed according to a second embodiment and depicted insuccessive stages of fabrication.

FIG. 3 is an integrated circuit containing an SRAM cell array whichincludes SRAM cells with T-shaped contacts formed according to oneembodiment.

DETAILED DESCRIPTION

The present invention is described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the invention.Several aspects of the invention are described below with reference toexample applications for illustration. It should be understood thatnumerous specific details, relationships, and methods are set forth toprovide an understanding of the invention. One skilled in the relevantart, however, will readily recognize that the invention can be practicedwithout one or more of the specific details or with other methods. Inother instances, well-known structures or operations are not shown indetail to avoid obscuring the invention. The present invention is notlimited by the illustrated ordering of acts or events, as some acts mayoccur in different orders and/or concurrently with other acts or events.Furthermore, not all illustrated acts or events are required toimplement a methodology in accordance with the present invention.

For the purposes of this disclosure, the term “static random accessmemory,” referred to hereafter as SRAM, is understood to mean any memoryin which data is stored in cells as voltage levels on cross-coupledinverters. SRAM cells are understood to include six-transistor cells,cells with separate read ports and write ports, cells with ferroelectriccapacitors, and any other memory cells with cross-coupled inverters.

In this disclosure, the term “driver transistor” is understood to referto a metal oxide semiconductor (MOS) transistor, possibly a field effecttransistor, a finFET transistor or a carbon nanotube transistor (CNT),in an SRAM cell. A drain node of the driver transistor is connected to adata node of the SRAM cell. A gate node of the driver transistor isconnected to an opposite data node of the SRAM cell from the driverdrain node. A source node of the driver transistor is connected to apower supply node, typically either Vdd for PMOS driver transistors orVss for NMOS driver transistors.

Similarly, the term “load transistor” is understood to refer to anotherMOS transistor, possibly a field effect transistor, a finFET transistoror a CNT, in the SRAM cell. A drain node of the load transistor isconnected to a data node of the SRAM cell. A gate node of the loadtransistor is connected to an opposite data node of the SRAM cell fromthe load drain node. A source node of the load transistor is connectedto a power supply node, typically either Vdd for PMOS load transistorsor Vss for NMOS load transistors. A polarity of the load transistor isopposite a polarity of driver transistors.

The term “passgate transistor” is understood to refer to yet another MOStransistor, possibly a field effect transistor, a finFET transistor or aCNT, in the SRAM cell, of which one source/drain node is connected to adata node of the SRAM cell and an opposite source/drain node isconnected to a corresponding data line of the SRAM cell. Similarly, theterm “access transistor” is understood to refer to an MOS transistor inthe SRAM cell, of which one source/drain node is connected to a datanode of the SRAM cell and an opposite source/drain node is connected toa read buffer transistor. For the purposes of this disclosure, use ofthe term passgate transistor will be distinguished from use of the termaccess transistor by a convention in which passgate transistors arenever connected to read buffer transistors while access transistors arealways connected to read buffer transistors.

In some instances of integrated circuits containing SRAM cell arrays,substantially all circuits in the integrated circuit are dedicated tooperation of the SRAM array. In these instances, circuits which providedata to be stored in the SRAM array and circuits which use data from theSRAM array are located outside the integrated circuit containing theSRAM array. In other instances of integrated circuits containing SRAMcell arrays, such as microprocessors, digital signal processors andwireless telephony controllers, the circuits which provide data to bestored in the SRAM array and the circuits which use data from the SRAMarray are located within the integrated circuit.

An SRAM cell in an integrated circuit may contain T-shaped contacts, inwhich each T-shaped contact provides an electrical connection between adrain node of a driver transistor and a drain node of a correspondingload transistor in one inverter and a gate of an opposite inverter,where the two inverters form cross-coupled inverters in the SRAM cell. Aphotolithographic exposure step for drain connecting segments of theT-shaped contacts connecting the drain nodes of the driver transistorsand the load transistors may be performed separately from aphotolithographic exposure step for the gate connecting segments of theT-shaped contacts connecting the inverter gates to the drain connectingsegments. In one embodiment, an inner corner of the intersection of eachgate connecting segment with its corresponding drain connecting segmentmay be laterally offset from a nearest end of the drain connectingsegment by an amount greater than 10 percent of a separation betweenopposite drain connecting segments within the SRAM cell, so as toincrease a separation of the gate connecting segments. In anotherembodiment, the inner corner of the intersection of each gate connectingsegment with its corresponding drain connecting segment may be laterallyoffset from the nearest end of the drain connecting segment by an amountgreater than one-third of a width of the gate connecting segment. In oneembodiment, each gate connecting segment may be substantiallyperpendicular to its corresponding drain connecting segment. In anotherembodiment, each gate connecting segment may be tilted with respect toits corresponding drain connecting segment. In a further embodiment,each gate connecting segment may have some curvature.

FIG. 1A through 1C are top views of a pair of cross-coupled inverters inan SRAM cell (1002) contained in an integrated circuit (1000), in whichT-shaped contacts are formed according to a first embodiment anddepicted in successive stages of fabrication. Referring to FIG. 1A, theSRAM cell (1002) includes a first driver/passgate active strip (1004)and a second driver/passgate active strip (1006). In some embodiments,the driver/passgate active strips (1004, 1006) may be n-type. In otherembodiments, the driver/passgate active strips (1004, 1006) may bep-type. The SRAM cell (1002) includes a first load active strip (1008)and a second load active strip (1010). The load active strips (1008,1010) are an opposite conductivity type from the driver/passgate activestrips (1004, 1006).

The SRAM cell (1002) includes a first inverter gate (1012) which crossesthe first driver/passgate active strip (1004) and the first load activestrip (1008). An area of the first driver/passgate active strip (1004)overlapped by the first inverter gate (1012) forms a channel region(1014) of a first driver transistor (1016) of the SRAM cell (1002). Anarea of the first load active strip (1008) overlapped by the firstinverter gate (1012) forms a channel region (1018) of a first loadtransistor (1020) of the SRAM cell (1002). The SRAM cell (1002) alsoincludes a first passgate gate (1022) which crosses the firstdriver/passgate active strip (1004). An area of the firstdriver/passgate active strip (1004) overlapped by the first passgategate (1022) forms a channel region (1024) of a first passgate transistor(1026) of the SRAM cell (1002). The first driver transistor (1016) andfirst load transistor (1020) are part of a first inverter of the SRAMcell (1002).

Similarly, the SRAM cell (1002) includes a second inverter gate (1028)which crosses the second driver/passgate active strip (1006) and thesecond load active strip (1010). An area of the second driver/passgateactive strip (1006) overlapped by the second inverter gate (1028) formsa channel region (1030) of a second driver transistor (1032) of the SRAMcell (1002). An area of the second load active strip (1010) overlappedby the second inverter gate (1028) forms a channel region (1034) of asecond load transistor (1036) of the SRAM cell (1002). The SRAM cell(1002) includes a second passgate gate (1038) which crosses the seconddriver/passgate active strip (1006). An area of the seconddriver/passgate active strip (1006) overlapped by the second passgategate (1038) forms a channel region (1040) of a second passgatetransistor (1042) of the SRAM cell (1002). The second driver transistor(1032) and second load transistor (1036) are part of a second inverterof the SRAM cell (1002).

During a manufacturing process, a dielectric layer (not shown) is formedon the top surface of the integrated circuit (1000) described supra.Then a layer of photoresist (not shown) is formed over the dielectriclayer. A first drain connecting segment patterned area (1044) of a firstT-shaped contact of the SRAM cell (1002) is formed by a firstphotolithographic exposure step so that the first drain connectingsegment patterned area (1044) overlaps the first driver/passgate activestrip (1004) over a drain node (1046) of the first driver transistor(1016), and also overlaps the first load active strip (1008) over adrain node (1048) of the first load transistor (1020). A second drainconnecting segment patterned area (1050) of a second T-shaped contact ofthe SRAM cell (1002) is also formed by the first photolithographicexposure step so that the second drain connecting segment patterned area(1050) overlaps the second driver/passgate active strip (1006) over adrain node (1052) of the second driver transistor (1032), and alsooverlaps the second load active strip (1010) over a drain node (1054) ofthe second load transistor (1036).

In another step of the manufacturing process, shown in FIG. 1B, a firstgate connecting segment patterned area (1056) of the first T-shapedcontact is formed by a second photolithographic exposure step so thatthe first gate connecting segment patterned area (1056) overlaps thesecond inverter gate (1028) and intersects the first drain connectingsegment patterned area (1044) so that an end of the first drainconnecting segment patterned area (1044) over the drain node (1048) ofthe first load transistor (1020) extends beyond the first gateconnecting segment patterned area (1056) by a first pattern lateraloffset distance (1058). In the instant embodiment, the intersectingedges of the first drain connecting segment patterned area (1044) andthe first gate connecting segment patterned area (1056) aresubstantially perpendicular.

Similarly, a second gate connecting segment patterned area (1060) of thesecond T-shaped contact is formed by the same second photolithographicexposure step so that the second gate connecting segment patterned area(1060) overlaps the first inverter gate (1012) and intersects the seconddrain connecting segment patterned area (1050) so that an end of thesecond drain connecting segment patterned area (1050) over the drainnode (1054) of the second load transistor (1036) extends beyond thesecond gate connecting segment patterned area (1060) by a second patternlateral offset distance (1062). In the instant embodiment, intersectingedges of the second drain connecting segment patterned area (1050) andthe second gate connecting segment patterned area (1060) aresubstantially perpendicular.

In one realization of the instant embodiment, the first pattern lateraloffset distance (1058) and the second pattern lateral offset distance(1062) may each be greater than 10 percent of an end separation distance(1064) between ends of the first drain connecting segment patterned area(1044) and the second drain connecting segment patterned area (1050). Inan alternate realization, the first pattern lateral offset distance(1058) may be greater than one-third of a width (1066) of the first gateconnecting segment patterned area (1056), and the second pattern lateraloffset distance (1062) may be greater than one-third of a width (1068)of the second gate connecting segment patterned area (1060).

The outer edges of the first load active strip (1008) and the secondload active strip (1010) are separated by a load active strip outerdistance (1070). Inner edges of the first gate connecting segmentpatterned area (1056) and the second gate connecting segment patternedarea (1060) are separated by a gate connecting segment patterned areainner distance (1072).

In another realization of the instant embodiment, an outer edge of thechannel region (1024) of the first passgate transistor (1026) may extendbeyond an outer edge of the channel region (1014) of the first drivertransistor (1016) by a first driver/passgate active offset distance(1074) which may be greater than half of the first pattern lateraloffset distance (1058). Similarly, an outer edge of the channel region(1040) of the second passgate transistor (1042) may extend beyond anouter edge of the channel region (1030) of the second driver transistor(1032) by a second driver/passgate active offset distance (1076) whichmay be greater than half of the second pattern lateral offset distance(1062).

In yet another step of the manufacturing process, shown in FIG. 1C, thefirst T-shaped contact (1078) is formed in an area defined by the firstdrain connecting segment patterned area (1044) and the first gateconnecting segment patterned area (1056) depicted in FIG. 1B. The firstT-shaped contact (1078) includes a first drain connecting segment (1080)in the area defined by the first drain connecting segment patterned area(1044) of FIG. 1B and a first gate connecting segment (1082) in the areadefined by the first gate connecting segment patterned area (1056) ofFIG. 1B. The first drain connecting segment (1080) makes electricalcontact to the drain node (1046) of the first driver transistor (1016)and to the drain node (1048) of the first load transistor (1020). Thefirst gate connecting segment (1082) makes electrical contact to thesecond inverter gate (1028). Thus, the first T-shaped contact (1078)provides an electrical connection between the drain node (1046) of thefirst driver transistor (1016), the drain node (1048) of the first loadtransistor (1020), and the second inverter gate (1028).

The second T-shaped contact (1084) is formed in an area defined by thesecond drain connecting segment patterned area (1050) and the secondgate connecting segment patterned area (1060). The second T-shapedcontact (1084) is formed concurrently with the first T-shaped contact(1078). The second T-shaped contact (1084) includes a second drainconnecting segment (1086) in the area defined by the second drainconnecting segment patterned area (1050) of FIG. 1B and a second gateconnecting segment (1088) in the area defined by the second gateconnecting segment patterned area (1060) of FIG. 1B. The second drainconnecting segment (1086) makes electrical contact to the drain node(1052) of the second driver transistor (1032) and to the drain node(1054) of the second load transistor (1036). The second gate connectingsegment (1088) makes electrical contact to the first inverter gate(1012). Thus, the second T-shaped contact (1084) provides an electricalconnection between the drain node (1052) of the second driver transistor(1032), the drain node (1054) of the second load transistor (1036), andthe first inverter gate (1012).

An end of the first drain connecting segment (1080) over the drain node(1048) of the first load transistor (1020) extends beyond the first gateconnecting segment (1082) by a first contact lateral offset distance(1090). An end of the second drain connecting segment (1086) over thedrain node (1054) of the second load transistor (1036) extends beyondthe second gate connecting segment (1088) by a second contact lateraloffset distance (1092). In one realization of the instant embodiment,the first contact lateral offset distance (1090) and the second contactlateral offset distance (1092) may each be greater than 10 percent of anend separation distance (1094) between ends of the first drainconnecting segment (1080) and the second drain connecting segment(1086). In an alternate realization, the first contact lateral offsetdistance (1090) may be greater than one-third of a width (1096) of thefirst gate connecting segment (1082), and the second contact lateraloffset distance (1092) may be greater than one-third of a width (1098)of the second gate connecting segment (1088).

The inner edges of the first gate connecting segment (1082) and thesecond gate connecting segment (1088) are separated by a gate connectingsegment inner distance (1100). In one realization of the instantembodiment, the first driver/passgate active offset distance (1074) maybe greater than half of the first contact lateral offset distance(1090), and the second driver/passgate active offset distance (1076) maybe greater than half of the second contact lateral offset distance(1092).

FIG. 2A through FIG. 2C are top views of a pair of cross-coupledinverters in an SRAM cell (2002) contained in an integrated circuit(2000), in which T-shaped contacts are formed according to a secondembodiment, depicted in successive stages of fabrication. Referring toFIG. 2A, the SRAM cell (2002) includes a first driver/passgate activestrip (2004), a second driver/passgate active strip (2006), a first loadactive strip (2008) and a second load active strip (2010) with theproperties described in reference to FIG. 1A. The SRAM cell (2002)includes a first inverter gate (2012) which crosses the firstdriver/passgate active strip (2004) and the first load active strip(2008). An area of the first driver/passgate active strip (2004)overlapped by the first inverter gate (2012) forms a channel region(2014) of a first driver transistor (2016) of the SRAM cell (2002). Anarea of the first load active strip (2008) overlapped by the firstinverter gate (2012) forms a channel region (2018) of a first loadtransistor (2020) of the SRAM cell (2002). The SRAM cell (2002) includesa first passgate gate (2022) which crosses the first driver/passgateactive strip (2004). An area of the first driver/passgate active strip(2004) overlapped by the first passgate gate (2022) forms a channelregion (2024) of a first passgate transistor (2026) of the SRAM cell(2002). The first driver transistor (2016) and first load transistor(2020) are part of a first inverter of the SRAM cell (2002). Similarly,the SRAM cell (2002) includes a second inverter gate (2028) whichcrosses the second driver/passgate active strip (2006) and the secondload active strip (2010). An area of the second driver/passgate activestrip (2006) overlapped by the second inverter gate (2028) forms achannel region (2030) of a second driver transistor (2032) of the SRAMcell (2002). An area of the second load active strip (2010) overlappedby the second inverter gate (2028) forms a channel region (2034) of asecond load transistor (2036) of the SRAM cell (2002). The SRAM cell(2002) includes a second passgate gate (2038) which crosses the seconddriver/passgate active strip (2006). An area of the seconddriver/passgate active strip (2006) overlapped by the second passgategate (2038) forms a channel region (2040) of a second passgatetransistor (2042) of the SRAM cell (2002). The second driver transistor(2032) and second load transistor (2036) are part of a second inverterof the SRAM cell (2002).

During a manufacturing process, a dielectric layer (not shown) is formedon the top surface of the integrated circuit (2000) of the secondembodiment, described supra. Then a layer of photoresist (not shown) isformed over the dielectric layer. A first drain connecting segmentpatterned area (2044) of a first T-shaped contact of the SRAM cell(2002) is formed by a first photolithographic exposure step so that thefirst drain connecting segment patterned area (2044) overlaps the firstdriver/passgate active strip (2004) over a drain node (2046) of thefirst driver transistor (2016), and also overlaps the first load activestrip (2008) over a drain node (2048) of the first load transistor(2020). A second drain connecting segment patterned area (2050) of asecond T-shaped contact of the SRAM cell (2002) is also formed by thefirst photolithographic exposure step so that the second drainconnecting segment patterned area (2050) overlaps the seconddriver/passgate active strip (2006) over a drain node (2052) of thesecond driver transistor (2032), and also overlaps the second loadactive strip (2010) over a drain node (2054) of the second loadtransistor (2036).

In another step of the manufacturing process, shown in FIG. 2B, a firstgate connecting segment patterned area (2056) of the first T-shapedcontact is formed by a second photolithographic exposure step so thatthe first gate connecting segment patterned area (2056) overlaps thesecond inverter gate (2028) and intersects the first drain connectingsegment patterned area (2044) so that an end of the first drainconnecting segment patterned area (2044) over the drain node (2048) ofthe first load transistor (2020) extends beyond the first gateconnecting segment patterned area (2056) by a first pattern lateraloffset distance (2058). In the instant embodiment, an end of the firstgate connecting segment patterned area (2056) overlapping the secondinverter gate (2028) is inclined toward the end of the first drainconnecting segment patterned area (2044) by a first pattern inclineddistance (2060) which may be greater than half of the first patternlateral offset distance (2058).

Similarly, a second gate connecting segment patterned area (2062) of thesecond T-shaped contact is formed by the same second photolithographicexposure step so that the second gate connecting segment patterned area(2062) overlaps the first inverter gate (2012) and intersects the seconddrain connecting segment patterned area (2050) so that an end of thesecond drain connecting segment patterned area (2050) over the drainnode (2054) of the second load transistor (2036) extends beyond thesecond gate connecting segment patterned area (2062) by a second patternlateral offset distance (2064). In the instant embodiment, an end of thesecond gate connecting segment patterned area (2062) overlapping thefirst inverter gate (2012) is inclined toward the end of the seconddrain connecting segment patterned area (2050) by a second patterninclined distance (2066) which may be greater than half of the secondpattern lateral offset distance (2064).

In one realization of the instant embodiment, the first pattern lateraloffset distance (2058) and the second pattern lateral offset distance(2064) may each be greater than 10 percent of an end separation distance(2068) between ends of the first drain connecting segment patterned area(2044) and the second drain connecting segment patterned area (2050). Inan alternate realization, the first pattern lateral offset distance(2058) may be greater than one-third of a width (2070) of the first gateconnecting segment patterned area (2056), and the second pattern lateraloffset distance (2064) may be greater than one-third of a width (2072)of the second gate connecting segment patterned area (2062).

In another realization of the instant embodiment, an outer edge of thechannel region (2024) of the first passgate transistor (2026) may extendbeyond an outer edge of the channel region (2014) of the first drivertransistor (2016) by a first driver/passgate active offset distance(2074) which may be greater than half of the end separation distance(2068). Similarly, an outer edge of the channel region (2040) of thesecond passgate transistor (2042) may extend beyond an outer edge of thechannel region (2030) of the second driver transistor (2032) by a seconddriver/passgate active offset distance (2076) which may be greater thanhalf of the end separation distance (2068).

Referring to FIG. 2C, the first T-shaped contact (2078) is formed in anarea defined by the first drain connecting segment patterned area (2044)and the first gate connecting segment patterned area (2056) depicted inFIG. 2B. The first T-shaped contact (2078) includes a first drainconnecting segment (2080) in the area defined by the first drainconnecting segment patterned area (2044) of FIG. 2B and a first gateconnecting segment (2082) in the area defined by the first gateconnecting segment patterned area (2056) of FIG. 2B. The first drainconnecting segment (2080) makes electrical contact to the drain node(2046) of the first driver transistor (2016) and to the drain node(2048) of the first load transistor (2020). The first gate connectingsegment (2082) also makes electrical contact to the second inverter gate(2028). Thus, the first T-shaped contact (2078) provides an electricalconnection between the drain node (2046) of the first driver transistor(2016), the drain node (2048) of the first load transistor (2020), andthe second inverter gate (2028).

The second T-shaped contact (2084) is formed in an area defined by thesecond drain connecting segment patterned area (2050) and the secondgate connecting segment patterned area (2062) depicted in FIG. 2B. Thesecond T-shaped contact (2084) is formed concurrently with the firstT-shaped contact (2078). The second T-shaped contact (2084) includes asecond drain connecting segment (2086) in the area defined by the seconddrain connecting segment patterned area (2050) of FIG. 2B and a secondgate connecting segment (2088) in the area defined by the second gateconnecting segment patterned area (2062) of FIG. 2B. The second drainconnecting segment (2086) makes electrical contact to the drain node(2052) of the second driver transistor (2032) and to the drain node(2054) of the second load transistor (2036). The second gate connectingsegment (2088) also makes electrical contact to the first inverter gate(2012). Thus, the second T-shaped contact (2084) provides an electricalconnection between the drain node (2052) of the second driver transistor(2032), the drain node (2054) of the second load transistor (2036), andthe first inverter gate (2012).

An end of the first drain connecting segment (2080) over the drain node(2048) of the first load transistor (2020) extends beyond the first gateconnecting segment (2082) by a first contact lateral offset distance(2090). In the instant embodiment, an end of the first gate connectingsegment (2082) overlapping the second inverter gate (2028) is inclinedtoward the end of the first drain connecting segment (2080) by a firstcontact inclined distance (2092) which may be greater than half of thefirst contact lateral offset distance (2090). An end of the second drainconnecting segment (2086) over the drain node (2052) of the second loadtransistor (2032) extends beyond the second gate connecting segment(2088) by a second contact lateral offset distance (2094). In theinstant embodiment, an end of the second gate connecting segment (2088)overlapping the first inverter gate (2012) is inclined toward the end ofthe second drain connecting segment (2086) by a second contact inclineddistance (2096) which may be greater than half of the second contactlateral offset distance (2094).

In one realization of the instant embodiment, the first contact lateraloffset distance (2090) and the second contact lateral offset distance(2094) may be each greater than 10 percent of an end separation distance(2098) between ends of the first drain connecting segment (2080) and thesecond drain connecting segment (2086). In an alternate realization, thefirst contact lateral offset distance (2090) may be greater thanone-third of a width (2100) of the first gate connecting segment (2082),and the second contact lateral offset distance (2094) may be greaterthan one-third of a width (2102) of the second gate connecting segment(2088).

FIG. 3 is an integrated circuit (3000) containing an SRAM cell array(3002) which includes SRAM cells (3004) with T-shaped contacts formedaccording to one embodiment. The SRAM cells (3004) are arranged in rows(3006) and columns (3008). Each word line bus (3010) is connected toSRAM cells (3004) in a row (3006). Each word line bus (3010) may includemore than one word line. Each bit line bus (3012) is connected to SRAMcells (3004) in a column (3008). Each bit line bus (3012) may includeone or more bit or bit-bar lines. A row decoder circuit (3014) appliesappropriate biases to word lines in the word line buses (3010). A columndecoder circuit (3016) applies appropriate biases to bit or bit-barlines in the bit line buses (3012). A data input/output (10) circuit(3018) reads data from the bit or bit-bar lines in the bit line buses(3012) during read operations and applies appropriate potentials to thebit or bit-bar lines in the bit line buses (3012) during single sidedwrite operations. The integrated circuit further includes a data bus(3020) which carries data bits between the data 10 circuit (3018) andcircuits in the integrated circuit (3000), and an address bus (3022)which is used to select SRAM cells (3004) in the SRAM cell array (3002)for read and write operations. The address bus (3022) is connected tothe row decoder circuit (3014) and the column decoder circuit (3016).The integrated circuit (3000) may also contain a data generation circuit(3024) which connects to the data bus (3020) and address bus (3022). Thedata generation circuit (3024) produces incoming data bits for storagein the SRAM cell array (3002). The data bus (3020) carries the incomingdata bits from the data generation circuit (3024) to the SRAM cell array(3002). The integrated circuit (3000) may also contain a data usagecircuit (3026) which connects to the data bus (3020) and address bus(3022). The data usage circuit (3026) uses outgoing data bits which werestored in the SRAM cell array (3002). The data bus (3020) carries theoutgoing data bits from the SRAM cell array (3002) to the data usagecircuit (3026).

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

1. An integrated circuit containing an array of SRAM cells, each said SRAM cell comprising: a first driver transistor of said SRAM cell of said array within said integrated circuit, said first driver transistor having a drain node and a channel region; a first load transistor, said first load transistor having a drain node and a channel region; a first inverter gate, said first inverter gate overlapping said channel region of said first driver transistor and overlapping said channel region of said first load transistor; a second driver transistor, said second driver transistor having a drain node and a channel region; a second load transistor, said second load transistor having a drain node and a channel region; a second inverter gate, said second inverter gate overlapping said channel region of said second driver transistor and overlapping said channel region of said second load transistor; a first T-shaped contact, further including: a first drain connecting segment, said first drain connecting segment overlapping said drain node of said first driver transistor and overlapping said drain node of said first load transistor; and a first gate connecting segment, said first gate connecting segment overlapping said second inverter gate and intersecting said first drain connecting segment; and a second T-shaped contact, further including: a second drain connecting segment, said second drain connecting segment overlapping said drain node of said second driver transistor and overlapping said drain node of said second load transistor; and a second gate connecting segment, said second gate connecting segment overlapping said first inverter gate and intersecting said second drain connecting segment, such that; an end of said first drain connecting segment overlapping said drain node of said first load transistor extends beyond said intersection of said first gate connecting segment by a distance greater than 10 percent of an end separation distance between ends of said first drain connecting segment and said second drain connecting segment; and an end of said second drain connecting segment overlapping said drain node of said second load transistor extends beyond said intersection of said second gate connecting segment by a distance greater than 10 percent of said end separation distance between said ends of said first drain connecting segment and said second drain connecting segment; wherein, an end of said first gate connecting segment overlapping said second inverter gate is inclined toward said end of said first drain connecting segment by a first inclined distance, said first inclined distance being greater than half said distance by which said end of said first drain connecting segment extends beyond said first gate connecting segment; and an end of said second gate connecting segment overlapping said first inverter gate is inclined toward said end of said second drain connecting segment by a second inclined distance, said second inclined distance being greater than half said distance by which said end of said second drain connecting segment extends beyond said second gate connecting segment.
 2. The integrated circuit of claim 1, further including: a first passgate transistor, said first passgate transistor having a channel region; and a second passgate transistor, said second passgate transistor having a channel region, such that; an outer edge of said channel region of said first passgate transistor extends beyond an outer edge of said channel region of said first driver transistor by a distance greater than half said distance by which said end of said first drain connecting segment extends beyond said first gate connecting segment; and an outer edge of said channel region of said second passgate transistor extends beyond an outer edge of said channel region of said second driver transistor by a distance greater than half said distance by which said end of said second drain connecting segment extends beyond said second gate connecting segment. 